1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory), and, more particularly, to a refresh control method for refreshing memory cells connected to an arbitrary number of word lines, the number being set in advance, in response to an input single refresh command.
2. Description of the Related Art
A DRAM achieves storage of data by storing charges in capacitors. Because the charges in a capacitor leak with the passage of time, it is necessary to refresh memory cells in a given cycle. In the refresh operation, word lines of a DRAM are activated in order to read data in those memory cells which are connected to the activated word lines via bit lines, a potential difference between the bit lines is amplified using a sense amplifier, and the resultant data is rewritten into the original memory cells.
The specifications on an auto refresh control method for a DDR (Double Data Rate) 2 DRAM or the like define the frequency of generation of an auto refresh command that a DRAM controller, which controls the refresh operation, provided outside the DRAM should generate. For example, it is defined in the specifications of the DDR2 DRAM that the DRAM controller should generate an auto refresh command at least once in every 7.8 microseconds.
From the viewpoint of the DRAM, the refresh operation should be performed inside the DRAM to hold data of all the memory cells in response to an auto refresh command input at least at a frequency of 7.8 microseconds.
Achievement of this refresh operation employs a configuration that simultaneously refreshes memory cells connected to a plurality of word lines every time a refresh command is input to each memory bank (see Japanese Unexamined Patent Application, First Publication No. 2003-187578).
FIG. 5 is a block diagram showing a configurational example of a conventional semiconductor memory device which performs such a refresh operation. The following will describe a case where the semiconductor memory device has eight memory banks BANK0 to BANK7.
When a refresh command REF is input to a DRAM controller (not shown) as a command CMD, a command receiver/decoder 140 generates a refresh command signal REFA in response to the refresh command REF and outputs the refresh command signal REFA to a refresh operation controller 150, an X address counter 122 and an X address selector/buffer 160. The refresh command signal REFA indicates execution of a refresh operation.
When a command ACT (Activate) is input as a command CMD, the command receiver/decoder 140 generates a signal ACTA and outputs the signal ACTA to the X address selector/buffer 160. The signal ACTA indicates selection of an address A0-A13 input from outside the DRAM controller via an address receiver 130.
When the refresh command signal REFA is input, the refresh operation controller 150 outputs refresh control signals REF0 to REF7 to respective memory banks 100 to 170. Those refresh control signals instruct the respective memory banks to refresh memory cells therein. The refresh operation controller 150 respectively outputs the refresh control signals REF0 to REF7 to the eight memory banks once or twice in response to one refresh command signal REFA input, as shown in timing charts which will be referred to in the following description. Specific examples of the operation of the refresh operation controller 150 will be described later referring to FIGS. 6 to 9.
Each word line in a memory bank to be refreshed is designated by an X address XADD which is the value of an X address (row address) held in the X address counter 122. The X address counter 122 counts up the value of the X address XADD by one every time the refresh command signal REFA is input.
A description will be given of a case where the value of the X address XADD held in the X address counter 122 is 0 and those memory cells in every memory bank which are connected to a word line designated by the X address XADD=0 are refreshed.
The X address selector/buffer 160 selects and outputs either the address A0-A13 input from outside the DRAM controller via the address receiver 130 or the X address XADD output from the X address counter 122.
When the refresh command signal REFA is input, the X address selector/buffer 160 selects the X address XADD output from the X address counter 122, and outputs the selected X address XADD to an X address latch 101 of every memory bank.
Each of the memory banks 100 to 170 respectively corresponding to the memory banks BANK0 to BANK7 refreshes memory cells in the memory banks based on the input X address XADD and the refresh control signals REF0 to REF7.
Referring now to timing charts shown in FIGS. 6 to 9, the description of the refresh operation of the semiconductor memory device shown in FIG. 5 will be given for four cases.
FIG. 6 is a timing chart illustrating the operation in the case where all of the eight memory banks are refreshed at the same time upon reception of the refresh command REF. Because all of the eight memory banks are refreshed simultaneously in FIG. 6, there arise a noise problem and a current problem both originated from a peak current.
FIG. 7 is a timing chart illustrating the operation in the case where upon reception of the refresh command REF, a half of the eight memory banks (BANK0 to BANK3) are refreshed first, and the remaining memory banks (BANK4 to BANK7) are refreshed after a given time elapses.
FIG. 8 is a timing chart illustrating the operation in the case where upon reception of the refresh command REF, the memory banks are refreshed sequentially every time a given time elapses.
Because the number of the memory banks to be refreshed simultaneously in FIGS. 7 and 8 becomes smaller than that in FIG. 6, the noise problem and the current problem both originated from the peak current are reduced.
In any of the cases in FIGS. 6 to 8, each memory bank refreshes memory cells connected to a single word line in response to a single refresh command REF input.
FIG. 9 is a timing chart illustrating the operation in the case where each memory bank refreshes those memory cells which are connected to two word lines in response to one refresh command REF input. To make an apparent improvement of the refresh efficiency of such a refresh operation, even when the capacity of the DRAM is increased, an auto refresh command which is input at the frequency of 7.8 microseconds can permit data in all the memory cells to be retained. In FIG. 9, however, noise generated becomes twice or so as large as noise in FIGS. 6 to 8, thus resulting in increased power consumption.
Consideration will be given to a relation between a data hold time tREF where data in memory cells can be retained without refreshing and the number, n, of word lines to be refreshed in accordance with a single auto refresh command (which hereinafter will occasionally be called “refresh word line number”).
For example, consideration will be given to a case where in a 1-G bits (64 M bits×16) DDR2 DRAM, 8192 (the number of word lines corresponding to a 13-bit row address)×8 (the number of banks)=64 K word lines are to be refreshed. As the time needed for refreshing all the word lines is 7.8 microseconds×64 K/n, the following equation 1 should be met.tREF≧7.8 microseconds×64K/n  (1)
As derived from the equation 1, when the data hold time tREF is 64 ms or longer, the number of word lines n can be 8, whereas when the data hold time tREF is 32 ms, the number of word lines n should be 16 (see FIG. 10).
In other words, when the number of word lines n is 16, the data hold time tREF needs to be 32 ms, whereas when the number of word lines is 8, the data hold time tREF needs to be 64 ms or longer.
The refresh word line number n should apparently be set equal to or greater than a certain number depending on the data hold time tREF. However, the refresh word line number n cannot be set indiscriminately large for a time tRFC from reception of the auto refresh command till completion of the auto refresh operation is determined by the specifications.
Assume a case where a refresh operation is performed for n word lines in a time-divisional manner while the word lines are activated one at a time. In this case, given that tRC is a time needed to refresh memory cells for one word line, the following equation 2 should be met.n×tRC≦tRFC  (2)
However, the specifications (standards) for tRC and tRFC define that the refresh word line number n is 3 or so at the maximum. If the time needed to perform a refresh operation for all the word lines exceeds the data hold time tREF, therefore, data in all the memory cells cannot be retained.
To increase the refresh word line number n, it is essential to operate a semiconductor memory device in manners explained above referring to FIGS. 6, 7, and 9. This operation however increases the peak current in proportion to the refresh word line number n, thus raising a problem of malfunction caused by noise which is originated from the increased peak current. Furthermore, the average consumed current during the auto refresh period becomes larger in proportion to the refresh word line number n, which is disadvantageous for the whole system using the DRAM from the viewpoint of the average consumed current.
As is apparent from the above, the refresh word line number n to be subjected to a refresh operation per a single auto refresh command should be determined in consideration of factors, such as the value of the data hold time tREF of the DRAM, the peak current at the time of refreshing, and the average consumed current.
FIG. 10 is a graph representing a relation between the refresh word line number n and the mentioned factors. In FIG. 10, the consumed current Ice is a relative value when the current value is set to 100% with the refresh word line number n being 8. As can be understood from FIG. 10, if the refresh word line number n can be changed arbitrarily in accordance with the data hold time tREF, the consumed current can be reduced by selecting a minimum refresh word line number n corresponding to the value of the data hold time tREF.
However, the configuration employed in the related art cannot arbitrarily set the value of the refresh word line number n. Changing the refresh word line number n in the related art is achieved by a method which degenerates a specific bit of the address (i.e., which does not use the specific bit as an address for a refresh operation) to simultaneously refresh memory cells connected to a plurality of word lines. In this case, the value of the refresh word line number n is limited to an integer multiple (multiple of 8) of the number of the memory banks.